The present invention relates to phase/frequency detectors and more particularly to an improved high speed phase/frequency detector.
Conventional phase/frequency detectors of the prior art used two bistable circuits, such as flip-flops, to detect the leading edges of first and second input signals applied thereto, such as a reference clock signal and a feedback pulse train found in phase locked loop circuit arrangements. The pulses out of the bistable circuits control respective intermediate transistor switching stages which switch constant current sources or current sinks off and on. This constitutes a charge pump arrangement which causes the current to be pumped into a storage device, such as a capacitor, and removed from the storage device, dependent upon the control pulses from the bistable circuits so as to produce an output voltage across the capacitor which is proportional to the phase or frequency difference between the first and second input signals. A reset pulse from a gate circuit, such as a NAND gate, is coupled to the bistable circuit outputs and is used to reset the bistable circuit immediately after both bistable circuits have been triggered on.
The problems with this type of phase/frequency detector and charge pump arrangement of the prior art are:
(1) Minimum reset pulse width to the charge pumps from the NAND gate is determined by the width necessary to reset both bistable circuits or flip-flops or the turn on/off times of the charge pumps. The minimum pulse width usually is too long and excessive clock feedthrough to the charge pumps' output occurs.
(2) Switching time of the single transistor charge pumps is slow (tens of nanoseconds) thus limiting the phase detectors' use to clock frequencies below one MHz (megahertz).
(3) The charge pump balance is set initially by a potentiometer in one of the switching arrangements. However, the current balance varies with temperature, supply voltage changes and mismatches of the turn on/off time constants of the switches. The resulting mismatch results in excessive clock feedthrough.
(4) There exists no convenient way of programming different currents without possibly upsetting charge pump balance or the on/off time constants of the charge pump switches. Without this balance, excessive clock feedthrough results.
(5) The circuit of the prior art must have its level shifting circuitry specially tailored with "speed up" capacitors to enhance the charge pump's switching speed. The tailored value must be changed for different phase detector gains and is somewhat temperature dependent.
(6) Noise appearing on the charge pump power supply is not isolated from the charge pump output.